Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

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Digital Logic Design Using Verilog pp 343–365 Cite as

Non-synthesizable Verilog Constructs and Testbenches

  • Vaibbhav Taraate 2  
  • First Online: 01 November 2021

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The chapter discusses about the inter-delay, intra-delay assignments and other non-synthesizable constructs useful during the testbenches. The chapter is useful to understand about the non-synthesizable constructs and how to check for the functional correctness of the design.

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Taraate, V. (2022). Non-synthesizable Verilog Constructs and Testbenches. In: Digital Logic Design Using Verilog. Springer, Singapore. https://doi.org/10.1007/978-981-16-3199-3_15

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Blocking and Non-blocking Assignment in Verilog

  • Assignment is only done in procedural block(always ot initial block)
  • Both combintational and sequential circuit can be described.
  • Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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verilog non blocking assignment with delay

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Delay in Assignment (#) in Verilog

Syntax : #delay

It delays execution for a specific amount of time, ‘delay’.

There are two types of delay assignments in Verilog:

Delayed assignment: #Δt variable = expression; // “ expression”  gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression;  // “expression” gets evaluated at time 0 but gets assigned to the “variable” after the time delay Δt

Note: #(delay) can not be synthesized. So we do not use #(delay) in RTL module to create delay. There are other methods which can be used to create delays in RLT module. #(delay) can be used in testbench files to create delays.

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  • Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog
  • Ports in Verilog Module
  • Synthesis and Functioning of Blocking and Non-Blocking Assignments.
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verilog transport delay in non-blocking and blocking assignment

  • Thread starter onion2014
  • Start date Apr 12, 2013
  • Apr 12, 2013

Member level 1

What is the difference between the following lines of code ? reg1<= #10 reg2 ; reg3 = # 10 reg4 ; can anyone explain the difference, from the view of verilog event queue? Thanks.  

Advanced Member level 3

Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes. If you had the follwoing code, and assuming reg1 was 1 and reg2 was 2: Code: begin $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2); reg1 = #10 reg2 ; reg2 = #10 reg1 ; $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2); end The first display statement would show the values 1 and 2, and 20 time units later the second $display statement would show the values 2 and 2. That is because the update to reg1 happens at time+10 before the second assignment statement executes. If you had Code: begin $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2); reg1 <= #10 reg2 ; reg2 <= #10 reg1 ; $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2); #10 $display("Display3 %1 reg1: %d, reg2: %d", $time, reg1, reg2); #1 $display("Display4 %1 reg1: %d, reg2: %d", $time, reg1, reg2); end The first two display statements would always display the same values for reg1 and reg2 at the same time regardless of the delay (the old values), and thew would both display in order at the same time. The third display statement will also the old values, but 10 time units later. The updates to the LHS occur after all the other things scheduled for that time slot have executed. The 4th display statement will display the updated values, 2 and 1. There is no good reason to use the blocking assignment with a delay.  

  • Apr 14, 2013

verilog non blocking assignment with delay

dave_59 said: Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes. If you had the follwoing code, and assuming reg1 was 1 and reg2 was 2: Code: begin $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2); reg1 = #10 reg2 ; reg2 = #10 reg1 ; $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2); end The first display statement would show the values 1 and 2, and 20 time units later the second $display statement would show the values 2 and 2. That is because the update to reg1 happens at time+10 before the second assignment statement executes. If you had Code: begin $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2); reg1 <= #10 reg2 ; reg2 <= #10 reg1 ; $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2); #10 $display("Display3 %1 reg1: %d, reg2: %d", $time, reg1, reg2); #1 $display("Display4 %1 reg1: %d, reg2: %d", $time, reg1, reg2); end The first two display statements would always display the same values for reg1 and reg2 at the same time regardless of the delay (the old values), and thew would both display in order at the same time. The third display statement will also the old values, but 10 time units later. The updates to the LHS occur after all the other things scheduled for that time slot have executed. The 4th display statement will display the updated values, 2 and 1. There is no good reason to use the blocking assignment with a delay. Click to expand...

For reg3 = # 10 reg4 ; next_statement; The right hand side is evaluated at the current time, then the assignment statement waits 10 time units. then makes an assignment to the left hand side, reg3. The next_statement executes after the assignment is made. A completely useless construct. Do not use it. reg3 <= # 10 reg4 ; next_statement; The right hand side is evaluated at the current time, The next_statement executes after the evaluation of the RHS. The assignment to reg3 is put in a queue to be ex executed 10 time unites later. Any delay in front of any statement might as well be thought of as an independent statement. so #10 reg3 = reg4l; behaves the same as #10; reg3 = reg4; Continuous assignments using the assign keyword do not have transport delays. They use inertial delays. What this means is the delay on a continuous assignment cannot be longer than the switching delays on the RHS. See the LRM section 10.3.3 Continuous assignment delays .  

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Verilog - Assignment 할당 구문 - blocking, non-blocking

Verilog 를 사용하는 할당 구문은 크게 =, <=  2개를 많이 사용하는데 헷갈릴까봐 일단 정리

Continuous Assigns

혹은 딜레이 요소를 넣어서 ( 물론 딜레이는 합성이 되지 않는다 )

Procedural Assignment

always 문이나 initial 문 안에서 사용되는 할당 문이다.

일단 2가지가 있다. blocking, non-blocking 일단 머 하드웨어의 기본은 non-blocking 이다.

C 코드가 아니므로, 순차적 실행은 존재할 수 없다.

blocking 은 대부분 그냥 combinational 회로로 대체되고, non-blocking 은 F/F, Latch 가 사용된다고 보면 된다.

A procedural assignment updates the value of register data types. Syntax: [ delay ] register_name = [ delay ] expression;     // blocking [ delay ] register_name <= [ delay ] expression;    // non-blocking

https://www.hdlworks.com/hdl_corner/verilog_ref/items/ProceduralAssignment.htm

https://verilogams.com/refman/modules/discrete-processes.html

assign (좌변) = (우변) ;   꼴로 작성을 하게 되는데 좌변에는 항상 wire type 변수 만이 올 수가 있습니 다.

reg 는 assign 문의 우변에는 올 수 있지만 좌변에 올 수 없습니다.

verilog non blocking assignment with delay

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verilog non blocking assignment with delay

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COMMENTS

  1. verilog intra delay for both blocking and non-blocking statement

    2 Answers Sorted by: 4 #1 x = y; means wait one tick then assign y to x. #1; x = y; means wait one tick then do nothing then assign y to x. Both statements behave identically. #1 x <= y; means wait one tick then sample y in the active region then assign x in the NBA region. #1; x <= y;

  2. PDF Verilog Nonblocking Assignments With Delays, Myths & Mysteries

    Verilog Nonblocking Assignments With Delays, Myths & Mysteries Clifford E. Cummings Sunburst Design, Inc. [email protected] ABSTRACT There is a common misconception that coding sequential logic with nonblocking assignments does not simulate correctly unless a #1delay is added to the right hand side of the nonblocking assignment operator.

  3. Verilog Inter and Intra Assignment Delay

    Verilog delay statements can have delays specified either on the left hand side or the right hand side of the assignment operator. Inter-assignment Delays // Delay is specified on the left side #<delay> <LHS> = <RHS> An inter-assignment delay statement has delay value on the LHS of the assignment operator.

  4. Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

    There are Two types of Procedural Assignments in Verilog. Blocking Assignments Nonblocking Assignments To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Blocking assignments (=) are done sequentially in the order the statements are written.

  5. Verilog Blocking & Non-Blocking

    Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a <= symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment.

  6. PDF Verilog Nonblocking Assignments with Delays

    reference T refers to the queue, ordered by and all events are if (there are inactive events) { activate all inactive events; activate all monitor events; } else { activate advance T to the next event time; }

  7. PDF Understanding Verilog Blocking and Nonblocking Assignments

    An edge-sensitive intra-assignment timing control permits a special use of the repeat loop. The edge sensitive time control may be repeated several times before the delay is completed. Either the blocking or the non-blocking assignment may be used. always always @(IN) @(IN) OUT OUT <= <= repeat.

  8. PDF Correct Methods For Adding Delays To Verilog Behavioral Models

    Adding delays to the left hand side (LHS) of any sequence of blocking assignments to model combinational logic is also flawed. The adder_t7a example shown in Figure 4 places the delay on the first blocking assignment and no delay on the second assignment. This will have the same flawed behavior as the adder_t1 example.

  9. PDF I. Blocking vs. Nonblocking Assignments

    1. Evaluate a | b, assign result to 2. Evaluate a^b^c, assign result to 3. Evaluate b&(~c), assign result to x y z end Nonblocking assignment: all assignments deferred until all right-hand sides have been evaluated (end of simulation timestep) always @ (a or b or c) begin x <= y <= z <= | b; ^ b ^ c; & ~c; 1. Evaluate a | 2. Evaluate a^b^c 3.

  10. verilog

    1 Answer Sorted by: 1 Register variables in Verilog represent flip-flops in hardware. The declaration: reg x; creates a single-bit register that can only hold the values: x (unknown), 0 or 1. The cl_tb.v code is attempting to assign values to register x that are too large to fit in a single bit value.

  11. Non-synthesizable Verilog Constructs and Testbenches

    15.2.3 Non-blocking Assignments with Inter-assignment Delays. Using the intra-assignment delays with the non-blocking assignment, it delays both the evaluation of the assignment and the update of the assignment. Consider the Verilog code shown in Example 5.

  12. Blocking, delayed assignment vs Non-blocking, delayed assignment on a

    Using non-blocking assignments, there is no delay between the successive @ (in) constructs, so every change on in gets caught. The change to out gets scheduled for 5 time units later for every change of in. That is the definition of transport delay. initial begin @ (in) output = #5 in; @ (in) output = #5 in; @ (in) output = #5 in; ...

  13. Blocking and Non-blocking Assignment in Verilog

    When working with behavioural modeling in Verilog, there are two types of assigment which is known as blocking and non blocking assigment and both of them there is a operator, '=' operator for blocking assignment and '<=' operator for non blocking assigment. At short, blocking assignment executes one by one sequentially and non-blocking ...

  14. Delay in Assignment (#) in Verilog

    Syntax: #delay. It delays execution for a specific amount of time, 'delay'. There are two types of delay assignments in Verilog: Delayed assignment: #Δt variable = expression; // " expression" gets evaluated after the time delay Δt and assigned to the "variable" immediately.

  15. verilog transport delay in non-blocking and blocking assignment

    Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes. The first ...

  16. verilog

    (x) in this code,assume 'a' gets changed from x to 0 initially. so always block gets triggered.while executing first statement compiler gets to know that it is non blocking statement, hence value of 'a' is assigned with temporary varibale but not yet assigned to 't'. since it is non blocking, parallely it executes second statement.but second sta...

  17. Verilog

    blocking 은 대부분 그냥 combinational 회로로 대체되고, non-blocking 은 F/F, Latch 가 사용된다고 보면 된다. A procedural assignment updates the value of register data types. Syntax: [ delay ] register_name = [ delay ] expression; // blocking [ delay ] register_name <= [ delay ] expression; // non-blocking

  18. nonblocking

    1 Answer Sorted by: 1 #10 a<=1; is equivalent to #10; a<=1; and #10; is a blocking statement. To make parallel you need non-blocking delay a<= #10 1; initial begin a<=0;b<=0; a<= #10 1; b<= #10 1; b<= #25 0; a<= #35 0; end Alternatively, you can put at the assignments in a fork-join.

  19. Blocking assignments in always block verilog?

    now I know in Verilog, to make a sequential logic you would almost always have use the non-blocking assignment (<=) in an always block. But does this rule also apply to internal variables? If blocking assignments were to be used for internal variables in an always block would it make it comb or seq logic?