verilog task forever

Forever Loop – Verilog Example

The keyword forever in Verilog creates a block of code that will run continuously. It is similar to other loops in Verilog such as for loops and while loops . The main difference between these and the forever loop is that the forever loop will never stop running, whereas for and while have a limit.

Forever Loops should not be used in synthesizable code . They are intended for use in simulation testbenches only. Forever loops are most useful within tasks . This allows a task to perform some functionality until the simulation is quit. Note that the Jump Statements return and break can be used to exit your loop prematurely, but these are only supported in SystemVerilog.

Make sure that your forever loop takes some delta time or it could hang your simulation!

forever_ex.v:

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SystemVerilog forever loop

A forever loop runs forever, or for infinite time.

A forever loop is similar to the code shown below in Verilog. Both run for infinite simulation time, and is important to have a delay element inside them.

An always or forever block without a delay element will hang in simulation !

In SystemVerilog, an always block cannot be placed inside classes and other SystemVerilog procedural blocks. Instead we can use a forever loop to achieve the same effect.

The pseudo code shown below mimics the functionality of a monitor in testbench that is once started and allowed to run as long as there is activity on the bus it monitors.

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Use of forever and always statements

Both the following codes generate a clock. I need to know if there is any use of forever loop other than clock generation? I have only come across forever in clock generation. If it only serves this purpose, isn't it useless?

3 Answers 3

Your second code snippet is actually a syntax error. The difference between forever and always is that always can exist as a "module item", which is the name that the Verilog spec gives to constructs that may be written directly within a module, not contained within some other construct. initial is also a module item. always blocks are repeated, whereas initial blocks are run once at the start of the simulation.

forever is a procedural statement that can only be used in a procedural context. So it is legal to write initial forever or always forever , but not just forever .

The situation where forever becomes quite important is within tasks, which are procedural contexts, so use of always is not allowed. (Functions are procedural contexts as well, but may not contain delays, which makes it unlikely that forever will come in useful.

Yes, forever loops have widespread usage in testbenches for design verification, particulalry in the industry standard methodology, UVM, and its predecessors (such as VMM). They are used in verification components such as drivers and monitors which make extensive use of tasks in SystemVerilog classes.

//i will show the difference;;;;;;; //we cannot use the forever block inside the initial block,but we can use forever block inside the intial block //code with error :

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Forever Loop in SystemVerilog

As the name suggests, a forever loop runs indefinitely. To terminate the loop, a break statement can be used.

forever loop Examples

Example with $finish.

To terminate the loop, $finish system call is used.

Please enable JavaScript

Example with a break statement

The break statement is used in the below example to terminate the loop based on the condition. The break statement will be discussed under the break and continue section .

Difference between always and forever block

Both always and forever block the same effect. The always block is a procedural block and it can not be placed inside other procedural blocks. Also, always block can not be used inside the class.

Syntax for always block:

Example of always block

A always block inside another procedural block.

A compilation error is expected when always block is used inside another procedural block. In such a case, a forever block can be used.

A always block inside a class

A compilation error is expected when always block is used inside a class. We will discuss the concept of class in the upcoming section.

forever loop inside a class

Now, replace always block with forever block.

System Verilog Tutorials

Verification Guide

SystemVerilog repeat and forever loop

Repeat and forever loop.

Table of Contents

repeat loop

repeat will execute the statements within the loop for a loop variable number of times.

if the loop variable is N , then the statements within the repeat block will be executed N number of times.

repeat loop syntax

statements 1-n will be executed for a variable value number of times.

repeat loop example

In the below example, repeat loop value is 4 , so the statements within the repeat loop will be executed for 4 times.

Simulator Output

Please enable JavaScript

forever loop

As the name says forever loop will execute the statements inside the loop forever. It can be said as indefinite iteration.

forever loop syntax

Forever loop example.

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[SOLVED]   system verilog forever loop

• Thread starter sumeet1990
• Start date Mar 18, 2015
• Mar 18, 2015

Newbie level 5

1) Code: module enum_test; enum {red,green,blue,yellow} c; initial begin c=c.first; forever begin $display("%s %d",c.name,c); if(c==c.last) break; c=c.next; end end endmodule 2) Code: module enum_test; enum {red,green,blue,yellow} c; initial begin c<=c.first; forever begin $display("%s %d",c.name,c); if(c==c.last) break; c<=c.next; end end endmodule 3) Code: module enum_test; enum {red,green,blue,yellow} c; initial begin c<=c.first; forever begin #10 //<<<<<-------------------things change by adding this $display("%s %d",c.name,c); if(c==c.last) break; c<=c.next; end end endmodule Hello, I am new to SV please help me with the codes above 1)In the first code I used forever loop with blocking assignments and with and timing procederals and everything works nicely.I get red,blue,green,yellow resp. 2)Int the second code I am using non blocking statements and while simulating it hangs the simulation by displaying "red","0" 3) in the third code I just added a delay and simulation works fine displaying values after specified delay Now, I now the working of blocking and non blocking assignments but just can get how it is working in the above codes. also, I don't quite get how this delay addition affects the code. thank you in advance  

Advanced Member level 2

You always need delays in an infinite loop having non blocking statements. Check below link.. https://stackoverflow.com/questions/13831883/stuck-in-while-loop-verilog  

thank you, that cleared my doubt in codes 1 and 2. But can you please explain what exactly happens after we add delay....i mean can you give me a line by line explanation after addition of delay in third code  

Super Moderator

sumeet1990 said: Now, I now the working of blocking and non blocking assignments Click to expand...

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How to finish the forever statement on run_phase in UVM?

I'm trying to understand forever statement in raise_objection()/drop_objection() . I thought that the forever statement will be finished after drop_objection() . But, the below forever statement does not finish.

So the simulation be hanged. It couldn't finish. What am I supposed to do to finish if I want to use forever statement in run_phase() ?

• system-verilog

• \$\begingroup\$ Your code does not make much sense so it is unclear what functionality you are looking for. The repeat loop would just overwrite each trans you are getting. Maybe you just need to move the q_trans_addr.push_back(trans.addr); as the last statement of the repeat loop, and remove the forever loop. You need to explain how it is supposed to operate before anyone could show you how to fix it. \$\endgroup\$ –  dave_59 May 27, 2022 at 16:51
• \$\begingroup\$ @dave_59 That's why I used m_analysis_fifo.get(trans); to prevent overwrite when I am getting. I understand that uvm_tlm_analysis_fifo is working as FIFO, why does The repeat loop would just overwrite trans? How to avoid the overwrite from it? Could you please guide me ? \$\endgroup\$ –  Carter May 31, 2022 at 6:11
• \$\begingroup\$ What kind of component is this? a scoreboard? what is put()ing into the analysis fifo, a monitor? and how are the put()s timed? what does #300 represent? \$\endgroup\$ –  dave_59 Jun 1, 2022 at 1:50

The forever block will never end. This means that you will never exit the block and never execute the drop_objection statement. Therefore, your test hangs.

Objections are not typically used in components ; they are typically used in tests (classes extended from uvm_test ). Remove the objection statements from your run_phase code:

However, that forever block is a zero-time infinite loop, which may still cause your simulation to hang. You would normally have some other statement in the block, like a wait or a delay.

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