assignment types vhdl

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Assign record to different type without conversion function in VHDL

Brief introduction to the issue I am trying to solve. I have type, which is a subtype of std_logic_vector , representing generic frame. I have also few record types, which represent specific types of frame.

I would like to be able to assign signals/variables of these types without calling conversion functions. I was thinking about 2 ways to achieve this.

Overload assignment operators. However it looks like custom overloading of assignment operators is not possible. I am not 100% as I failed to find this explicitly being said in the standard, but I think so because I have found no examples of such overloading in the IEEE library source codes.

Make specific frame record types a subtypes of t_frame type. It looks like declaring a record as a subtype is also not possible. I have found no examples in the standard.

Does anyone know if it is possible to assign record to different type without conversion function in VHDL?

• 1 \$\begingroup\$ Assignment is not an operator, to answer Q1.. One hack I've seen used in Ada is to overload a convenient unary operator like "+" (since "+ x" is idempotent with "x") with your conversion functions. Should work equally well in VHDL. Not perfect but "keeps the noise down a bit". \$\endgroup\$ –  user16324 Apr 5, 2020 at 14:29
• \$\begingroup\$ You mean that assignment is not an operator in VHDL, but assignment in other languages usually are operators, aren't they? By the way the trick with unary operators works, at least in GHDL. Thanks. \$\endgroup\$ –  Al Bundy Apr 5, 2020 at 15:59
• \$\begingroup\$ The concept of operators comes from mathematics : an operator produces a result without altering any of its arguments. (This allows operators to be treated in special ways, reordering, optimisations, etc without affecting correctness of results). Thus assignment cannot be an operator. But you are correct that some languages are sloppy and get this wrong... \$\endgroup\$ –  user16324 Apr 5, 2020 at 16:34
• 2 \$\begingroup\$ The two assignments (without conversion) - t_frame_obj <= t_frame_x_obj.a & t_frame_x_obj.b; and t_frame_x_obj <= (a => t_frame_obj(23 downto 20), b => t_frame_object(19 downto 0); Your question has elements of an XY problem and a Yes/No question. \$\endgroup\$ –  user8352 Apr 5, 2020 at 18:47
• \$\begingroup\$ @user8352 The shown example is trivial just to show the problem. The records I use have much more fields and using the concatenation method you have presented is tedious and error prone (in the sense of typing mistake). \$\endgroup\$ –  Al Bundy Apr 5, 2020 at 19:26

To answer the question directly:

Is it possible to assign a record to a different type without conversion function in VHDL?

No, you will need to write a custom conversion function, or split the assignment out manually as per the comment by @user8352. As you say, this looks messy and is error prone, so a custom conversion function (probably inside a package) is the way to go.

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Variables vs. Signals in VHDL

Variables and Signals in VHDL appears to be very similar. They can both be used to hold any type of data assigned to them. The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol. However the differences are more significant than this and must be clearly understood to know when to use which one. If you need a refresher, try this page about VHDL variables .

Signals vs. Variables:

• Variables can only be used inside processes, signals can be used inside or outside processes.
• Any variable that is created in one process cannot be used in another process, signals can be used in multiple processes though they can only be assigned in a single process .
• Variables need to be defined after the keyword process but before the keyword begin . Signals are defined in the architecture before the begin statement.
• Variables are assigned using the := assignment symbol. Signals are assigned using the <= assignment symbol.
• Variables that are assigned immediately take the value of the assignment. Signals depend on if it’s combinational or sequential code to know when the signal takes the value of the assignment.

The most important thing to understand (and the largest source of confusion) is that variables immediately take the value of their assignment, whereas signals depend on if the signal is used in combinational or sequential code . In combinational code, signals immediately take the value of their assignment. In sequential code, signals are used to create flip-flops, which inherently do not immediately take the value of their assignment. They take one clock cycle. In general, I would recommend that beginners avoid using variables. They can cause a lot of confusion and often are hard to synthesize by the tools.

The example below demonstrates how signals behave differently than variables. Notice that r_Count and v_Count appear to be the same, but they actually behave very differently.

Variables can be a bit tricky to display in simulation. If you are using Modelsim, read more about how to see your variables in Modelsim’s waveform window . Look carefully at the waveform above. Do you see how o_var_done pulses every 5th clock cycle, but o_sig_done pulses every 6th clock cycle? Using signals and variables to store data generates very different behavior . Make sure you clearly understand what you code will be generating and make sure that you simulate your code to check that behaves like you want!

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VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

• unsigned-integer

3 Answers 3

See other answers, and note that for non-zero literals, you probably want to do something like:

Substitute a literal for n . This works for n =0 too, of course, but it's not as tidy as (others => '0') .

• LCD_DATA'LENGTH isn't available until after the semicolon. IEEE Std 1076-1993 10.3 Notes "2—The rules defining immediate scope, hiding, and visibility imply that a reference to an identifier, character literal, or operator symbol within its own declaration is illegal (except for design units). The identifier, character literal, or operator symbol hides outer homographs within its immediate scope—that is, from the start of the declaration. On the other hand, the identifier, character literal, or operator symbol is visible only after the end of the declaration (again, except for design units)." –  user1155120 Mar 18, 2014 at 23:02
• For -2008 that's Section 12.3 Visibility, same Note 2. –  user1155120 Mar 18, 2014 at 23:16
• The original erroneous answer provided variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, LCD_DATA'length); Essentially something isn't available until it is declared and the declaration is variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; , which is where the after the semicolon comment comes from. See IEEE Std 1076-1993 4.3.1.3 (6.4.2.4 -2008) Variable declarations. –  user1155120 Mar 18, 2014 at 23:26
• Yeah, I'm so used to using that construct in processes, etc., I forgot it was illegal in declarations. –  fru1tbat Mar 19, 2014 at 13:53

And for the 2nd part of your question while adding number of this type.

Check whether you have used above libraries in the code or not.

unsigned is related to std_ulogic, where the value for an element would be '0'.

which provides an aggregate for the default assignment with all elements set to '0'.

You can't assign a single element of integer type to an array of std_ulogic elements.

You can add signed or unsigned to a natural (unsigned) or integer (signed) using "+" functions defined in package numeric_std:

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